Verilog HDL Project

I am looking for someone who is professional in Verilog HDL. You should be using VIVADO software to support me in the project, and the project has to be functional on BASYS3 board. Make a project with multiple modules. You can choose the project yourself, but I will provide some initial suggestions. Nothing is too hard or complicated. If you have VIVADO and BASYS3 board then you should be fine. We can discuss more about it in the chat or once I confirm the tutor. I can extend the deadline as well.

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