1) A sequential circuit with two D flip-flops A and B, two inputs, x and y, and one output z is
specified by the following next-state and output equations: (10 point)
??+1 = ??
′ + ??
??+1 = ?? + ??
′
? = ?
a) Draw the logic diagram of the circuit.
b) List the state table for the sequential circuit.
c) Draw the corresponding state diagram.
2) A sequential circuit has two JK flip-flop A and B and one input x. The circuit is described by the
following flip-flop input equations: (15 point)
?? = ? ?? = ?
?? = ? ?? = ?
′
a) Derive the state equations ??+1 and ??+1 by substituting the input equations for the J
and K variables.
b) Draw the state diagram of the circuit.
3) A sequential circuit has three flip-flops A, B, C; one
input ???; and one output ????. The state diagram is
shown in next figure. The circuit is to be designed by
treating the unused states as don’t care conditions.
Analyze the circuit obtained from the design to
determine the effect of unused states. (15 point)
a) Using D flip-flops
b) Using T flip-flops
4) Design a sequential circuit with two D flip-flops A
and B, and one input ???. (15 point)
a) When ??? = 0, the state of the circuit remains the same. When ??? = 1, the circuit goes
through the state transitions from ?? → ?? → ?? → ?? → ?? and repeats the
sequence.
b) When ??? = 0, the state of the circuit remains the same. When ??? = 1, the circuit
goes through the state transitions from ?? → ?? → ?? → ?? → ?? and repeats the
sequence.
5) Design a four-bitshift register with parallel load using D flip-flops. There are two control inputs:
shift and load. When shift = 1, the content of the register is shifted by one position. New data are
transferred into the register when load = 1 and shift = 0. If both control inputs are equal to 0, the
content of the register does not change. (10 point)
6) Draw the logic diagram: (15 point)
a) A four-bit register with four D flip-flops and four
4 × 1 multiplexers with mode selection inputs 1 and 0.
The register operates according to the following
function table.
b) A four-bit binary ripple countdown counter using
flip-flops that trigger on the positive-edge of the clock.
c) A timing circuit that provides an output signal that stays on for exactly twelve clock
cycles. A start signal sends the output to the 1 state, and after twelve clock cycles the
signal returns to o state.
7) Using D flip-flops: (20 point)
a) Design a counter with the following repeating binary sequence ? → ? → ? → ? → ?.
Draw the logic diagram of the counter.
c) Design a counter with the following repeated binary sequence 0 → ? → ? → ? → ?.
Draw the logic diagram of the counter