ELEC340 Digital Design introduction to VHDL coding, follow lab requirements below fairly easy.
At the end of lab, turn in a PDF file showing all of your pre-lab and lab work as required below
Within the lab:
1. Fill in the truth tables provided within the lab. (You can scan the lab or just truth tables as
your solution.)
Include the following with your lab:
2. Screenshot showing full zoomed-in simulation of the SOP design for all possible input
combinations
3. Copies of your VHDL code including the testbed and relevant sections of the constraints
file.
DETAILED ASSIGNMENT
