NOTE: Before you start answering the questions, please use your own words and avoid plagiarism at all. All the answers are in the textbook.

Q1. To compete more effectively, your organization is considering a profit sharing plan to increase employee effort and to encourage employees to think like owners. What are the potential advantages and disadvantages of such a plan? Would the profit sharing plan have the same impact on all types of employees? Is the size of your organization an important consideration? Why? What alternative pay programs should be considered? (CH10)

Q2. Your company plans to build a new manufacturing plant but is undecided where to locate it. What factors would you consider in choosing in which country (or state) to build the plant?? (CH11)

Q3. What types of skills do you need to be able to manage in today’s global marketplace? Where do you expect to get those skills? What classes and/or experiences will you need?? (CH15)

Q4: Why are many managers reluctant to coach their employees? (CH9)

Q5. Why have the roles and activities of the HRM function changed over the past 20–30 years? What has been driving this change? How effectively do you think HRM has responded? (CH16)

Q6: How might imaging technology be useful for recruitment? For training? For benefits administration? For performance management? (CH16)

Assignment 3                                                                                

Students are requested to read the opening case of chapter 9 “Protecting Innovation” from their book Strategic Management of Technological Innovation (Page Number-197-200) of e-textbook. Based on your understanding of the case and concepts studied until now answer the following question in 300-500 words each.

1. What industry conditions led to the revolution in audio distribution described above? Which stakeholders stand to benefit most (or least) from this revolution?

2. Why did the music stores created by the record labels fail to attract many subscribers? What, if anything, should the record labels have done differently?

3. What factors led iTunes to be successful?

4. How do you think a move away from owning music led to record-setting music revenues?

You are to write a one-two page memo to Bob Henderson. In that memo you are to make two recommendations:

If the city of Big Valley were to continue to use Oracle/PeopleSoft, who would you recommend for maintenance? Why?

• Oracle

• Accenture

• Legacy Mode

• Tomorrow Now

Regardless of the recommendation that you provided above, what is your recommendation for the city of Big Valley regarding their ERP system? Should they stay with Oracle, move to GEMS, or move to IFAS? Why?

Assignment Question(s): (Marks:5)

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Writ a critical analysis on subprime crisis that had hit the United State financial market in 2007-2008 and had severely affected powerful economies of the world. Please include the following points in your writing.

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• Introduction of the crisis

• Causes of the crisis

• Whom to blame, Basel II, rating agency, the regulators or the banks themselves.

• Conclusion.

DETAILED ASSIGNMENT

20210406173327assignment_2__fin_301_

Problem 1 [20 pts]

The purpose of this problem is to familiarize you with the synthesis and place and route process and to give you a rough feeling for the size of a few simplecircuits. Turn in a detailed report with the results for each part. o For all designs register the inputs and outputs, and add timing constraint for the clock (e.g 400 MHz=2.5ns). Check the Slack, if it couldn’t make the timing constraint, slow down the clock until it meets the timing. Report the final clock period and frequency that the design can results to near zero slack (<0.15 ns). o Synthesize and place and route the following blocks and report their total slice count, and BRAM, registers and other resource counts. Make sure you include registers (flip-flops) at the input and output and constrain the timing path as explained in the class. No need to write testbench and simulate, only turn in the source verilog, but your verilog must compile correctly. o After Implementation report the power dissipation of each block for your clock specification that the design can operate. Note that for power number, your design clock must be set to the number that you found in previous step, and Implementation step must be done again. o Report your results in a table. Report the numbers in a single table so it can be used as a note sheet in the future. o Include verilog files for each circuit in the report. o Include the generated schemetic under Implementation in your report. Blocks

a) [10 pts] two input 10-bit adder (11-bit output). Use “+” in verilog.

b) [10 pts] 20-bit by 20-bit unsigned multiplier (40-bit output). Use “*” in Verilog.

Problem 2 [40 pts]

Design a circuit that computes the product of 128 element-vectors, a and b; that is a vector p such that pi=ai*bi (i= 0 to 127). The elements of a and b are stored in separate SSRAMS and the result p is to be written into a third SSRAM. Assume that computation is started by a control signal, go when goes high for one cycle. Then when the computation of all 128 elements is complete, the done signal is to be set to one. Assume a and b are 16-bit values. Design

i.[5 pt] Draw the detailed block diagram with naming the signals

ii. [10 pt] Design a control state machine in verilog for controlling the signals and report these: 1. Control Sequence/steps (page 7 of State Machine slides) 2. Table for control signals (Page 8) 3. State diagram or Transition Function (Page 11 and 16)

iii. [15 pt] Write verilog for the SSRAM memories, datapath and statemachine to have a complete system. Behavioral Simulations iv. [5 pt] Write a testbench and simulate the design Implementation Results [5 pt] v. Perform Synthesis and Place and Route (Implementation) steps and vi. Report maximum clk that the design can achieve by adding timing constraints and minimum slack timing. vii. Report total slice count, and other FPGA resource counts viii. Report the power consumption at the frequency that it can work

Problem 3 [40 pts]

Design a FIFO to store up to 256 data items of 16-bits each, using 256x 16-bit dual-port SSRAM for the data storage. Assume the FIFO will not be read when it is empty, not to be written when it is full, and that the write and read ports share a common clock. Design

i. [5 pt] Draw the detailed block diagram with naming the signals

ii. [10 pt] Design a control state machine in verilog for controlling the signalsand report these: 1. Control Sequence/steps (page 7 of State Machine slides) 2. Table for control signals (Page 8) 3. State diagram or Transition Function (Page 11 and 16)

iii. [15 pt] Write verilog for the SSRAM memories, datapath and statemachine tohave a complete system. Behavioral Simulations iv. [5 pt] Write a testbench and simulate the design Implementation Results [5pts] v. Perform Synthesis and Place and Route (Implementation) steps and vi. Report maximum clk that the design can achieve by adding timing constraints and minimum slack timing. vii. Report total slice count, and other FPGA

Task: You will write an argumentative research paper of 4000–4500 words. “The argumentative research paper consists of an introduction in which the writer clearly introduces the topic and informs his audience exactly which stance he intends to take; this stance is often identified as the thesis statement. An important goal of the argumentative research paper is persuasion, which means the topic chosen should be debatable or controversial” (The Writing Lab and The OWL at Purdue, 2018). This assignment also has the goal of being multidisciplinary, which means that the evidence addressing the argument must be critically analyzed from at least two disciplinary viewpoints/perspectives. (“Interdisciplinarity” is the higher level of this approach, in which two disciplines work together at the level of method.) Your paper will be formatted according to the instructions listed in the Formatting section below.

DETAILED ASSIGNMENT

20210406173500intructions_and_rubric

In Java please

Create a method that is called priorityPush where it would be added to the code below. The goal of this method is to either add a new element to the stack or if the element already exists in the stack then move it up to the top and prioritize it.

the method header is:

public boolean priorityPush(T element)

I am looking for someone who is professional in Verilog HDL. You should be using VIVADO software to support me in the project, and the project has to be functional on BASYS3 board. Make a project with multiple modules. You can choose the project yourself, but I will provide some initial suggestions. Nothing is too hard or complicated. If you have VIVADO and BASYS3 board then you should be fine. We can discuss more about it in the chat or once I confirm the tutor. I can extend the deadline as well.

1. Find the equation of the circle with radius 9 and its center at the origin.
A. x
2
+ y
2
= 1
B. x
2
+ y
2
= 9
C. x
2
+ y
2
= 18
D. x
2
+ y
2
= 81
2. The equation of a circle is (x – 7)2
+ (y + 5)2
= 36. What is the location of the center of the
circle?
A. (−7, −5)
B. (−7, 5)
C. (7, −5)
D. (7, 5)
3. Identify a three-dimensional shape with two parallel and identical polygonal bases connected by
a lateral surface area.
A. Pyramid
B. Cone
C. Prism
D. Cylinder

DETAILED ASSIGNMENT

20210407045735geom_q4_pre_assess_a